![]() The four inputs are 8-but busses I 0, I 1, I 2 and I 3. The design consists of a 2-to-4 line decoder on the left side, with two single-bit selection inputs, S 1 and S 0. S 1 S 0 Y 0 0 I I I I 3 Table 1: 4-to-1 Line Multiplexer Condensed Truth Table The implementation of the 4-to-1 line multiplexer is illustrated in Figure 1. ![]() For the selected input line, the output will be equal to the value of the input (Mano and Kime, 150). A condensed version, given in Table 1, illustrates the possible values for selector variables S 1 and S 0 and the corresponding input variable I that is chosen to pass the data. The factored expression is as follows: Y = (~S 1 ~S 0 )I 0 + (~S 1 S 0 )I 1 + (S 1 ~S 0 )I 2 + (S 1 S 0 )I 3 The complete truth table for a 4-to-1 line multiplexer consists of 16 rows. Although the gate-input cost of the second expression is higher at 22, this implementation facilitates expansion of the circuit to include more inputs (Mano and Kime, 151). Traditionally, this equation is factored to construct a slightly different implementation of the multiplexor. ![]() Formulation and Optimization: The Boolean expression for a 4-to-1 line multiplexer is as follows: Y = ~S 1 ~S 0 I 0 + ~S 1 S 0 I 1 + ~S 1 ~S 0 I 2 + S 1 S 0 I 3 The gate-input cost to implement this expression is 18. A multiplexer (MUX) is a combinational circuit that utilizes selection inputs to choose binary information from multiple inputs and directs it to a single output (Mano and Kime, 149). 1 Project Part I 8-bit 4-to-1 Line Multiplexer Specification: This section of the project outlines the design of a 4-to-1 multiplexor which takes two 8-bit buses as inputs and produces a single 8-bit bus as output. ![]()
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